(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to processes used to improve the electrical contact between metal filled vias and metal interconnect structures.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of silicon devices and circuits, while still attempting to maintain, or decrease the manufacturing cost of silicon chips, comprised of these higher performing silicon devices and circuits. Micro-miniaturazation, or the ability of the semiconductor industry to create silicon devices with sub-micron features, has allowed the performance, as well as the cost, objectives to be met. Sub-micron device features result in performance improvements via decreases in parasitic capacitances, and resistances. In addition smaller device features allow the silicon chip size to be reduced, resulting in a greater number of silicon chips to be realized from a specific size substrate, thus reducing the manufacturing cost of a specific chip. The attainment of micro-miniaturazation has been highlighted by advances in specific semiconductor fabrication disciplines, such as photolithography, as well as reactive ion etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images in photoresist layers to be routinely achieved. In addition, advances in dry etching, or reactive ion etching, (RIE), have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials, used for the fabrication of advanced silicon devices.
The use of sub-micron features, although allowing the performance and cost objectives of the semiconductor industry to be realized, does present specific fabrication problems, not encountered for the fabrication of silicon devices using less aggressive designs. For example conventional approaches restrict the size of a contact or via, so that it comfortably falls on an underlying metal structure. This fully landed contact, or via, is usually made smaller than the width of the underlying metal structure by the amount of photolithographic misalignment allowed in the process. To take advantage of the micro-miniaturazation breakthroughs, these contacts or vias are now created with sub-micron dimensions. This brings about the problem of filling sub-micron vias with metal. The use of chemically vapor deposited tungsten, to fill sub-micron vias, is being used for via fills, taking advantage of the ability of tungsten to sustain high current densities without risking electromigration failure. However the mechanism of filling narrow diameter holes with CVD metals, results in a seam or void, at the center of the metal fill. This seam or void, when subjected to subsequent process steps, such as dry etching, used to form a metal plug in the narrow diameter hole, can evolve into a defect that can result in topology problems for subsequent overlying metallization structures. Many solutions for the metal seam phenomena have been described. For example Cheffings, et al, in U.S. Pat. No. 5,387,550, describe a process for filling voids or seams, in tungsten filled contact holes, with silicon. Marangon, et al, in U.S. Pat. No. 5,407,861, describe a process for minimizing the seam, by using a novel etch back process, to create the tungsten plug, without subjecting the exposed seam to additional dry etching procedures.
The process described in this invention will use a different approach. This invention will show a method of maintaining packing densities by reducing the size of the underlying metal structure, while increasing the size of the overlying metal filled via. The amount of contact area between the overlying metal filled via, and the underlying metal structure, is increased by removal of some passivation insulator from the sides of the underlying metal structure, making these exposed sides available for contact from the subsequent overlying, metal filled via. This approach, of using wider metal filled vias, reduce the seam problem, encountered with narrower via counterparts.